Electrical and Computer Engineering ETDs
Publication Date
Summer 7-31-2024
Abstract
The execution behavior of a Microprocessor (μP) in the presence of a fault is difficult to predict because of the complex interactions across pipeline stages and between functional units within the architecture. Fault effects are known to not introduce any type of anomaly in the input-output behavior for 10s of thousands to millions of clock cycles. These characteristics increase the difficulty of evaluating μP architectures for resilience to information leakage events, i.e., scenarios where a fault causes sensitive data such as an encryption key to be inadvertently diverted to a primary output channel. This dissertation explores two promising strategies for periodic testing for fault detection in μPs known as self-assertion-based countermeasures and counter-based periodic testing.
Keywords
FPGA, Cryptography, AES, IPsec, Security, Emulation, Testing, ATPG
Document Type
Dissertation
Language
English
Degree Name
Computer Engineering
Level of Degree
Doctoral
Department Name
Electrical and Computer Engineering
First Committee Member (Chair)
Jim Plusquellic
Second Committee Member
Eirini Eleni Tsiropoulou
Third Committee Member
Payman Zarkesh-Ha
Fourth Committee Member
Kofi Nyarko
Recommended Citation
Somoye, Idris. "Periodic Information Leakage Fault Detection on a RISC-V Microprocessor." (2024). https://digitalrepository.unm.edu/ece_etds/656
