Chemical and Biological Engineering ETDs
Through-silicon vias (TSVs) are a key interconnect technology for advanced packaging of microelectronic devices, and full wafer thickness TSVs are required for certain microelectromechanical systems (MEMS) applications. In this work, electrolytes containing copper sulfate, an acid, chloride, and Tetronic 701 suppressor were implemented for Cu filling of high aspect ratio (10:1), full wafer thickness TSVs. For each electrolyte system, rotating disk electrode voltammetry was used to identify a voltage range for bottom-up Cu filling in the TSVs. Die level feature filling was performed using voltage ramping, which moved active deposition through the vias to yield void-free Cu features. During voltage-controlled deposition experiments, current was measured, and a characteristic current minimum was identified, which is presented as a process endpoint detection method for TSV Cu filling.
To transition these Cu plating processes from the die to wafer level, experiments were performed to identify parameters required for wafer level plating. Since wafer level electroplating tools often do not have reference electrodes, a current-controlled deposition method was developed at the die level. To scale the deposition process from small 1 cm2 samples to a full wafer, multi-die scaling experiments were performed to evaluate how current scales with active plating area. Since vias along a rotating wafer’s radius have different linear velocities, rotation rate studies were conducted to observe the relationship between fluid flow and Cu fill profile. Future work will transition these results to a wafer level plating capability to produce full wafer thickness Cu-filled TSVs for MEMS and other microelectronics applications.
TSVs, through-silicon vias, MEMS, Copper, Electrodeposition, Electroplating, Heterogeneous Integration
Sandia National Laboratories
Level of Degree
Chemical and Biological Engineering
First Committee Member (Chair)
Second Committee Member
Third Committee Member
Schmitt, Rebecca P.. "COPPER ELECTRODEPOSITION IN FULL WAFER THICKNESS THROUGH-SILICON VIAS." (2020). https://digitalrepository.unm.edu/cbe_etds/88
Available for download on Monday, December 12, 2022