Electrical and Computer Engineering ETDs

Publication Date

Summer 7-29-2025

Abstract

Application Specific Integrated Circuit (ASIC) designs continue to scale with ever increasing complexity and device counts in the billions. Demand for scalable high-fidelity simulations of these systems drives the need for the development of novel modeling capabilities. This research formulates a non-intrusive model order reduc-tion (MOR) framework, called PUF-ROMS, to accelerate and optimize the design and analysis of physical unclonable functions (PUFs) on ASICs. The primary goals of PUF-ROMS are to estimate entropy and temperature-voltage noise (TV-noise) of circuit structures used in the design in an accelerated evaluation environment to enable designers to explore architecture options with the goal of maximizing entropy and minimizing the adverse impact of TV-noise on accessing this entropy. PUF-ROMS starts with the development of reduced order models (ROMs) for the logic cell primitives used in the PUF circuit structure. The cell primitive ROMs are then used in SPICE system-level Monte Carlo (MC) simulations to enable efficient exploration of the PUF design space, including improvements in both utility and performance.

Keywords

Cryptography, PUF, Machine Learning, Semiconductor Device Modeling, Hardware Security, Reduced Order Modeling

Sponsors

Sandia National Laboratories

Document Type

Dissertation

Language

English

Degree Name

Computer Engineering

Level of Degree

Doctoral

Department Name

Electrical and Computer Engineering

First Committee Member (Chair)

Jim Plusquellic

Second Committee Member

Payman Zarkesh-ha

Third Committee Member

Eirini Tsiropoulou

Fourth Committee Member

Biliana Paskaleva

Fifth Committee Member

Mitchell Martin

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