Electrical and Computer Engineering ETDs

Publication Date

Fall 11-16-2023


We investigate a novel side-channel attack countermeasure called Side-channel Power analysis Resistance for Encryption Algorithms using Dynamic partial reconfiguration (SPREAD). The countermeasure leverages a strategy that is best characterized as a moving target architecture. Modern field-programmable gate array (FPGA) architectures provide support for dynamic partial reconfiguration (DPR), a feature that allows real-time reconfiguration of portions of the programmable logic (PL) while the FPGA continues to carry out computing tasks. Using the Advanced Encryption Standard (AES), the proposed moving target architecture leverages DPR to change the implementation characteristics of the substitution boxes (SBOX) in real time. We present experimental hardware results that demonstrate increasing resistance to correlation power analysis (CPA) attacks as a function of different diversity types. We show that functional diversity provides the largest increase in CPA resistance, but it must be combined with netlist diversity and a moving target architecture to be an effective countermeasure.


side-channel attack countermeasure, FPGA dynamic partial reconfiguration, implementation diversity, moving target architecture, SBOX, AES

Document Type




Degree Name

Computer Engineering

Level of Degree


Department Name

Electrical and Computer Engineering

First Committee Member (Chair)

Dr. Jim Plusquellic

Second Committee Member

Dr. Eirini Eleni Tsiropoulou

Third Committee Member

Dr. William Zortman