Electrical and Computer Engineering ETDs

Publication Date

Spring 5-15-2021

Abstract

In this thesis, a novel shift register-based physical unclonable function (PUF), called SRP, is proposed. The PUF is implemented on an FPGA and leverages the internal delay variations introduced by within-die process variations that occur within the Look-up tables (LUTs), routing and switches of the FPGA. PUFs are designed to generate bitstrings and keys on-the-fly that are device-specific (unique), random and reproducible. PUFs eliminate the need for a specialized (secure) non-volatile memory(NVM) to store the secret keys. This reduces the total cost of chips and systems, particularly those used in the Internet of Things, where it is common for systems to be small, vulnerable and resource-constrained. Unlike previously proposed PUFs, many of which are based on ring oscillators (ROs) constructed from a series of inverters, the SRP uses the shift register capabilities of FPGA LUTs as the source of entropy. In our preliminary work, we construct a circuit that the ’rings’ in the spirit of the RO PUF, but accomplish this without inverters. This feature saves significant real estate because each inverter requires a dedicated LUT. Therefore, the SRP is very compact because only a single LUT is required to implement the inversions required for the circuit to ring. An alternative, very fast, launch-capture architecture is also explored that eliminates the requirement to ’ring’ the circuit as a means of extracting its entropy.

Keywords

PUFs, Hardware Security, Side-channel attack, cryptography, FPGA

Document Type

Thesis

Language

English

Degree Name

Computer Engineering

Level of Degree

Masters

Department Name

Electrical and Computer Engineering

First Committee Member (Chair)

Prof. Jim Plusquellic

Second Committee Member

Prof. Eirini Eleni Tsiropoulou

Third Committee Member

Prof. Payman Zarkesh-Ha

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