Electrical and Computer Engineering ETDs
Publication Date
Spring 4-14-2021
Abstract
A novel countermeasure to side-channel power analysis attacks called Side-channel Power analysis Resistance for Encryption Algorithms using DPR or SPREAD is investigated in this thesis. The countermeasure leverages a strategy that is best characterized as a moving target architecture. Modern field programmable gate arrays (FPGA) architectures provide support for dynamic partial reconfiguration (DPR), a feature that allows real-time reconfiguration of the programmable logic (PL). The moving target architecture proposed in this work leverages DPR to implement a power analysis countermeasure to side-channel attacks, the most common of which are referred to as differential power analysis (DPA) and correlation power analysis (CPA). The goal of the SPREAD technique is to reduce the power transient signal correlations associated with repeated use of the cryptographic key during encryption operations by dynamically changing the logic level hardware implementation of the cryptographic engine in real time.
Keywords
Countermeasure, FPGA, Side Channel Attacks, SCA, CPA, DPR
Document Type
Thesis
Language
English
Degree Name
Computer Engineering
Level of Degree
Masters
Department Name
Electrical and Computer Engineering
First Committee Member (Chair)
Dr. James Plusquellic
Second Committee Member
Dr. Payman Zarkesh-Ha
Third Committee Member
Dr. Eirini Eleni Tsiropoulou
Recommended Citation
Joseph, Jithin. "Side Channel Attack Counter Measure using a Moving Target Architecture." (2021). https://digitalrepository.unm.edu/ece_etds/558
Included in
Digital Circuits Commons, Electrical and Electronics Commons, Hardware Systems Commons, Other Computer Engineering Commons, VLSI and Circuits, Embedded and Hardware Systems Commons
