Electrical and Computer Engineering ETDs

Publication Date

Fall 12-19-2017

Abstract

DRAMATIC advances in the field of computational and medical imaging over the past decades have enabled many critical applications such as night vision, medical diagnosis, quality control, and remote sensing. The increasing demand for image quality and its fidelity requires an increase in pixel count and a sophisticated post-processing mechanism to efficiently store, transmit, and analyze this massive data. There is an inherent trade-off between the generation of big data by such imaging systems and efficiency in extraction of useful information within real-time constraints, limiting the efficacy of such sensors in real-time decision-making systems. The traditional imaging system gets burdened by the acquisition, transmission, and storage of surplus data, often bearing redundant information for the given application of interest. Transmission of the irrelevant information requires a high bandwidth and results in consuming extra power to store or transmit. Similarly, post-processing imposes extra latency and suffers under the power constraint, which is troublesome for many low-power, real-time applications, and portable devices. There is a need to address this problem by intelligently acquiring a limited but most important set of data features, and then efficiently processing this abstract information. This, in turn, needs an additional ability of performing computations at the pixel level, within the readout integrated circuit at the front-end of the imager. The most challenging job in this computational part is devising the mechanism to properly select the right set of data features for adequately representing the information which might be corrupted with noise and therefore potentially increase the reconstruction error. In this thesis, we work towards development of an efficient bias selection algorithm to configure the computational imaging hardware. This algorithm not only fulfills the fundamental hardware requirements of memory efficiency, low power consumption and minimal latency, but also results in lesser reconstruction error than the previously used naive approach. This algorithm supports compression during the data acquisition time at the pixel level thus enabling compression even in a noisy environment. This work was carried out in joint collaboration and supervision of two pioneers, Prof. Majeed Hayat and Prof. Paymen Zarkesh-Ha, under whom an integrated hardware and algorithm imaging concept called compressed domain imaging device was developed. The hardware used in this study was developed under the supervision of Prof. Payman Zarkesh-Ha by Dr. Javad Ghasemi, a graduate student from his lab. Details of this ``Readout Integrated Circuit" (ROIC) based imaging hardware are presented in Dr. Ghasemi's Ph.D. dissertation. The developed hardware enables compressed-domain image acquisition by means of projecting the input image onto a series of coded apertures, or spatial intensity masks, that are stored in the ROIC. The real-time, pixel-level projection is achieved by the means of designing a set of coded apertures and programming them in the ROIC as a 2D array of analog biases. The stored bias values at each pixel govern the operating point of the photodetector, thereby affecting the spatial intensity modulation of the image. The pixel values are then summed up within the ROIC. The output of this unique camera is therefore the features (or code-words) arising from the projection of the image onto each of the prescribed coded apertures. Hence, the camera does not generate and store the actual image at any point.The image can be reconstructed using a reconstruction algorithm that employs the features computed by the camera. However, due to the limited dynamic range and sensitivity of the hardware towards the noise, the overall performance could degrade significantly during computation of the Discrete Cosine Transform (DCT) and Compressed Sensing (CS) coefficients for data compression; hence the significance and applicability of the unique hardware could diminish considerably at times. This specific type of hardware limitation has opened the scope for this thesis work, where we have performed theoretical and experimental systematic study of the hardware by modeling its response and characterizing the noise statistically. Thus, in this work we develop a robust Minimum Mean Square Error (MMSE) based bias selection algorithm to overcome the effect of noise and formally demonstrate how use of superior signal processing techniques on the statistical model of the hardware response enhances the performance of computational imaging hardware systems.

Keywords

Bias Selection Algorithm, MMSE, Compressed Sensing, DCT, Computational Imaging, ROIC

Sponsors

National Science Foundation(NSF)

Document Type

Thesis

Language

English

Degree Name

Electrical Engineering

Level of Degree

Masters

Department Name

Electrical and Computer Engineering

First Committee Member (Chair)

Dr. Majeed M. Hayat

Second Committee Member

Dr. Payman Zarkesh Ha

Third Committee Member

Dr. Marios Pattichis

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