Electrical and Computer Engineering ETDs

Publication Date

Spring 4-5-2017

Abstract

As standard CMOS technology approaches its physical limitations there is increased motivation to explore new computing paradigms. One possible path forward is to develop an array of computational architectures which specialize in distinct tasks. Neural computing architectures excel at pattern recognition and processing low-fidelity sensory input, but one of the biggest challenges in the field has been implementing architectures which strike an appropriate balance between biologically-plausible performance and the simplicity needed to make large neural systems practical. This work proposes a new VLSI neural architecture which seeks to provide such a balance.

The design described here builds on an implementation first proposed by van Schaik. Van Schaik’s circuit has the advantage of simplicity. It uses a Leaky-Integrate-and-Fire model while offering some biologically analogous behavior and maintaining a very compact layout profile. However, the circuit lacks the ability to emulate certain desirable biologically inspired features, most notably spike frequency adaptation (SFA).

The circuit depicted receives a current stimulus as its input. If the current is greater than the neuron’s leakage current, then it charges a capacitor which drives a comparator circuit. When the voltage on the capacitor exceeds the threshold voltage a spike is generated. The design makes use of four parametric inputs to tune its behavior and also contains circuitry for a tunable refractory period and SFA.

Rather than operate in biological time, the circuit operates in accelerated time with a spike frequency in the nano-second region. This allows smaller capacitors to be used and reduces the overall layout area. The circuit layout was created using Tanner EDA’s L-Edit software and designed for fabrication with a 180nm technology node. It occupies 386.497µm2. The circuit was extracted and simulated using Tanner Tools T-Spice. Simulations show an average power consumption in the micro-Watt range.

Keywords

SFA, neural networks, leaky integrate and fire, VLSI

Document Type

Thesis

Language

English

Degree Name

Computer Engineering

Level of Degree

Masters

Department Name

Electrical and Computer Engineering

First Committee Member (Chair)

Payman Zarkesh-Ha

Second Committee Member

Thomas Caudell

Third Committee Member

Jim Plusquellic

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