Electrical and Computer Engineering ETDs

Publication Date

7-9-2008

Abstract

Spot defects represent the main challenge for enhancement of semiconductor manufacturing yield. As a result, the yield of modern integrated circuits is associated with the layout sensitivity to defects. The term layout sensitivity' is defined as the ratio of 'critical area', i.e. part of the layout in which a defect must be placed to cause a functional failure of the device, to the overall layout area. Semiconductor yield models are traditionally based on the analysis of the 'critical area'. Such models give accurate results; however, critical area analysis requires massive computations that render these models effort and time consuming. The stochastic method of yield modeling presents a much faster and easier approach. This thesis contributes to the stochastic method of yield modeling by offer-ing an efficient model that predicts the layout sensitivity to defects using very basic lay-out information. The model has some imperative applications that can expedite the yield analysis and prediction for modern VLSI designs. The prime application is pre-layout yield prediction. Using the proposed model, yield prediction can be performed even before starting the costly phase of layout design. Another application is yield forecasting and prediction of defect density requirements for future manufacturing technologies not yet developed. Fi-nally, the simplicity of the model allows its use during automatic cells placement to enhance the yield. A 'yield-aware automatic cells placement tool' is implemented. This thesis tackles also the subject of semiconductors reliability. We derive a model that predicts the layout sensitivity to interconnect 'narrow defects', i.e., missing material defect causing the formation of a narrow site in the victim interconnect without resulting in a disconnection in a signal path. Narrow defects favor electromigration, a major inter-connect failure mechanism, that makes narrow interconnects very likely to cause functional failure during operation in the field. The model is used to estimate the average number of narrowing defects in the layout.'

Document Type

Thesis

Language

English

Degree Name

Computer Engineering

Level of Degree

Masters

Department Name

Electrical and Computer Engineering

First Committee Member (Chair)

Abdallah, Chaouki

Second Committee Member

Hawkins, Charles

Third Committee Member

None

Download

Share

COinS