Electrical and Computer Engineering ETDs
Publication Date
4-15-1997
Abstract
A majority of today's sequential circuits implemented with Very Large Scale Integrated (VLSI) circuit technology are based on synchronous design. Asynchronous designs often result in better solutions, especially in applications dealing with low power electronics and asynchronous input changes. However, asynchronous sequential circuit design theory is not widely understood and, asynchronous designs are hindered by complex design procedures. Additionally, design complications such as critical races and hazards affect asynchronous sequential circuits but not synchronous sequential circuits.
Synchronous circuits, although widely used, are also subject to serious design limitations in VLSI implementations. Delays in the clock distribution network must be considered in today's high speed circuits. Additionally, peak power transients are high due to node switching during the clock edge.
Binary Tree Structure (BST) pass transistor networks have some practical design benefits such as the elimination of static, dynamic and delay hazards. These properties, in conjunction with partitioning theory and new design techniques, result in new designs for speed-independent asynchronous sequential circuits.
In this dissertation, new design methods are developed for speed-independent asynchronous sequential circuits using BTS pass transistor logic. The design procedures are simple and easy to implement. The resulting VLSI circuits can successfully process input transitions and can be programmed for automated design.
This dissertation presents the following:
1. Explanation of pass transistor logic and asynchronous sequential circuits.
2. Identification of new properties of Single Transition Time (STT) state assignments.
3. Proposal and development of four unique speed-independent designs.
4. Comparison of the new designs to an existing speed-independent design.
Document Type
Dissertation
Language
English
Degree Name
Engineering
Level of Degree
Doctoral
Department Name
Electrical and Computer Engineering
First Committee Member (Chair)
Gary Maki
Second Committee Member
Illegible
Third Committee Member
L. Howard Pollard
Fourth Committee Member
Illegible
Recommended Citation
Kaplan, John J.. "Speed-Independent Asynchronous Sequential Circuit Design." (1997). https://digitalrepository.unm.edu/ece_etds/796