Nanoscience and Microsystems ETDs

Publication Date

Summer 7-14-2017


Copper (Cu) electrodeposition (ECD) in through-silicon-vias (TSVs) is an essential technique required for high-density 3-D integration of complex semiconductor devices. The importance of Cu ECD in damascene interconnects has led to a natural development towards copper electrodeposition in TSVs. Cu ECD is preferred over alternative approaches like the chemical vapor deposition (CVD) of tungsten (W) or aluminum (Al) because Cu ECD films have lower film stress, lower processing temperatures, and more optimal thermal and electrical properties as compared with CVD W or Al.

Via filling with electroplated Cu on substrates that have undergone atomic layer deposition of a conformal platinum seed metal is investigated herein. These mesoscale vias (600 μm depth, 5:1 aspect ratio) will be utilized in ultra-high-vacuum systems and thus require a uniform, void-free Cu deposit of sufficient thickness to prevent device degradation due to skin effects when RF frequencies as high as 100 V at 100 MHz are used. Conformally Cu-lined TSVs are achieved through the implementation of a complex ECD parameter scheme, and these results are compared with computational finite element modeling (FEM) outcomes. A novel, single additive chemistry is also developed and implemented to achieve fully filled void-free mesoscale TSVs within 6 hours of plating time, which represents an extraordinarily fast and controllable plating rate (100 μm/hour) for interconnect (IC) feature filling.


Copper Through-Silicon-Vias TSV TSVs Electrodeposition Mesoscale

Document Type




Degree Name

Nanoscience and Microsystems

Level of Degree


Department Name

Nanoscience and Microsystems

First Committee Member (Chair)

Sang M. Han

Second Committee Member

Plamen Atanassov

Third Committee Member

Dimiter Petsev