Three-dimensional (3D) stacking of integrated circuits (ICs) is an enabling technology in the advancement of the microelectronics industry. 3D stacking enables increased device density per volume and improved electrical performance through short vertical interconnect paths. Mechanical reliability of 3D IC packages is critical due to the widespread use of electronic devices. Misalignment induced shear deformation of the through-silicon vias (TSV) and solder micro-bumps are simulated through an applied shearing action. Thermal effects due to coefficient of thermal expansion (CTE) mismatch during processing are also studied to provide trends of stress and deformation fields. Reliability of the 3D chip stack, TSV and solder micro-bump are assessed by examining local stresses and the buildup of plastic strain through series of parametric twodimensional (2D) and 3D finite element method (FEM) simulations. A special case when the solder joint is transformed into an intermetallic compound is also examined. Misalignment induced shearing strongly influences stresses and deformation in and around the micro-bump. Thermal CTE mismatches influence stresses and deformation in the entire 3D chip stack and in the TSV far away from the joint. Shortcomings of the 2D plane strain model for examining CTE mismatch and measuring buildup of plastic strain in the joint are also discussed.
Multichip modules (Microelectronics), Interconnects (Integrated circuit technology), Solder and soldering, Deformation (Mechanics)Plasticity, Plasticity.
Level of Degree
First Committee Member (Chair)
Second Committee Member
Johnson, Richard. "Numerical analysis of TSV/micro-bump deformation due to chip misalignment and thermal processing in 3D IC packages." (2012). https://digitalrepository.unm.edu/me_etds/64