Electrical and Computer Engineering ETDs

Publication Date

Summer 7-15-2020


Radio Frequency (RF) interference is a prominent issue for modern electronic devices. As device size and supply power shrink to meet the on-going demand for compact and complex Integrated Circuits (ICs), their susceptibility to external noise coupling to the input or power supply increases significantly. One such type of noise that acts upon a system to be considered is Extreme Electromagnetic Interference (EEMI). Previous works done to understand and evaluate the impact of EEMI onto a system or sub-system have been conducted on a statistical or empirical analysis level, which has led to complex and convoluted analysis, that requires significant time and computational power. Furthermore, since Electromagnetic Interference/Compatibility (EMI/EMC), engineers have to deal with complex systems, they typically come up with an estimate to analyze such systems.

The premise behind this research is to highlight the development of the refinements of such "rule-of-thumb" guidelines to help EMI/EMC engineers quickly estimate device or circuit level susceptibility for the injected EEMI signals. A novel analytical model is proposed in this research, which offers an alternative solution for the limits of malfunction for a Silicon-based (Si) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) under EEMI bias.

These developed analytical predictive models help determine the maximum limits for large-signal gate-side (input) or drain-side (power supply) injection in terms of the device's ION/IOFF ratio prior to degradation or damage to the device. The ION/IOFF ratio is a function based on the MOSFETs' device parameters. These models have been developed for a single transistor, particularly n-type and p-type MOSFETs when the EEMI signal is superimposed onto the gate or drain terminals. Additionally, these predictive models have also been extended to determine the maximum tolerance for gate or drain injections as transistor technology scales down. Furthermore, these models have been compared and validated with prototype test chips across five different technology nodes.

Lastly, the analytical models have been expanded to be used in several different assessments, such as high-frequency analysis, manufacturer, and transistor size-independent and sensitivity modeling. Such demonstrations show the fundamental nature and flexibility, which allows these models to be used based on the EMI/EMC engineers' needs.


Complementary metal–oxide–semiconductor (CMOS), electromagnetic interference (EMI), metal–oxide–semiconductor field-effect transistors (MOSFET), predictive modeling of nonlinear transistors, radio frequency (RF) effects, VLSI system

Document Type




Degree Name

Electrical Engineering

Level of Degree


Department Name

Electrical and Computer Engineering

First Committee Member (Chair)

Dr. Payman Zarkesh-Ha

Second Committee Member

Dr. Edl Schamiloglu

Third Committee Member

Dr. Sameer Hemmady

Fourth Committee Member

Dr. Daryl Beetner