Electrical and Computer Engineering ETDs

Author

Preyom Dey

Publication Date

6-26-2015

Abstract

The demand of extremely long battery life for electronic devices is the driving force for modern semiconductor industry in recent years. Supply voltage scaling offers a promising solution for this matter. To control the energy consumption and limit the power dissipation of a circuit, supply voltage should be scaled continually. Threshold voltage should also be reduced to sustain performance and reliability. This scaling of supply and threshold voltage imposes several bottlenecks in ultra-low voltage circuit design. One of the major barriers for ultra-low voltage design is the performance deviation of digital circuit due to supply voltage variation. As technology scales, channel length, width and threshold voltage variation of the device during processing, also effect the digital circuits characteristics. In this thesis, analytical models are derived to study the impact of process parameters and supply voltage variations on digital circuit. Based on these models, a projected 22nm process technology is used to examine the effects of device parameter variation on ultra-low voltage digital circuit's dynamic and static behaviors. High to low propagation delay variation and noise margin (high and low) variation of an inverter are investigated. Analytical simulation results are compared with T-Spice simulation as well to verify the accuracy of the analytical models. Monte Carlo method is used on a set of 1000 samples for T-Spice simulation. Results obtained by implementing our analytical models in MATLAB are similar to the T-Spice simulation results. Both simulation results confirm that the reduction of supply voltage increases the delay and noise margin variations in an inverter circuit. Noise margin (high) variation in an inverter is more sensitive to the process related issues than noise margin (low) variation. Another most important challenge for ultra-low voltage circuit design is to reduce the sub-threshold leakage power. A new circuit level design technique is presented in this thesis to tackle this issue. This technique allows bulk CMOS circuits to work in the sub-0.6V supply territory. The new design technique is compared with two existing leakage power reduction techniques. T-Spice simulation results suggest that, our new design can reduce the leakage power without compromising the delay of the circuit significantly. Also, our new proposed energy efficient design is more tolerant to process parameters and supply voltage variation effects. In the case of noise margin (high and low) of an inverter circuit, this new design technique is more beneficial to use than the conventional design.'

Keywords

Ultra Low Voltage Design

Document Type

Thesis

Language

English

Degree Name

Electrical Engineering

Level of Degree

Masters

Department Name

Electrical and Computer Engineering

First Advisor

Zarkesh-Ha, Payman

First Committee Member (Chair)

Balakrishnan, Ganesh

Second Committee Member

Sharma, Ashwani

Third Committee Member

Zarkesh-Ha, Payman

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