Electrical and Computer Engineering ETDs

Publication Date



The perennial need for memory storage is further increasing with the advancements in technology. Both terrestrial and space related applications thrive on efficient ways and new technology for storing data that is incorruptible and dependable. Research is continuously carried out on making storage systems vast and reliable. The development of 3D integration has spawned the idea of a new generation of memory based on 3D stackable chips. In an era where there is a continuous demand for larger, faster, denser and robust memories, 3D stackable memory settles in perfectly. However, technology scaling is having a negative effect on the robustness (low yield and higher sensitivity to radiation effects) of the memories and 3D stackable memory is no exception. As the eagerness for using 3D stackable memory builds up because of its many advantages the major concern that stands as an obstacle for such a system is its yield and system reliability. It is an important consideration in critical applications related to space, avionics, and defense. Even if a single memory domain fails in a stack of memory modules due to any kind of irregularity, it can lead to a total system breakdown. The potential dangers for 3D memory include destructive errors such as physical errors in memory arrays, wear out faults, hard errors (e.g. stuck bits) & errors due to memory yield problems and non-destructive errors (soft errors) such as single event upsets (SEU). There is also an increased risk of the 3D technology class memories to be effected by multiple bit upsets (MBU) because of their natural vertical structure. Hence, 3D memory needs an efficient memory controller that can make the memory more reliable and robust against such dangers. The memory controller should not only accomplish the memory accessing, but it also should act as a potential healing system (ability to retrieve the data and exclude the failed memory) for the stack of memory. The concentration of the present work is focused on 3D Nand flash memory. It proposes an efficient and robust memory controller for 3D Integrated Nand flash memory chips used in space radiation environment that performs continuous self test and repair. It revives the system from all single point hard errors and soft errors. The controller uses a novel and flexible memory mapping scheme (using PUF technology) and appropriate Error correction code (ECC) to protect against the above mentioned errors. The controller is implemented on a FPGA with three different kinds of ECC differing in the correction capability, space requirement, latency (delay) and power requirement. This work serves as a look up table for space missions with varying mission requirements to make the choice of a particular type of ECC to go with the 3D Nand flash controller.


3D Memory, Memory Controller, Space Radiation


Configurable Space Microsystems Innovations and Applications Center

Document Type




Degree Name

Electrical Engineering

Level of Degree


Department Name

Electrical and Computer Engineering

First Advisor

Zarkesh-Ha, Payman

First Committee Member (Chair)

Lyke, James

Second Committee Member

Plusquellic, James F.