![Engineering ETDs](../../assets/md5images/35609176e540f2adf5588d644e84911b.jpg)
Electrical and Computer Engineering ETDs
Publication Date
7-2-2011
Abstract
Variations in delay caused by within-die and die-to-die process variations and SOI history effect increase timing margins and reduce performance. In order to develop mitigation techniques to reduce the detrimental effects of delay variations, particularly those that occur within-die, new methods of measuring delay variations within actual products are needed. The data provided by such techniques can also be used for validating models, i.e., can assist with model-to-hardware correlation. In this research work, a method is proposed for a flush delay technique to measure both regional delay variations and SOI history effect. The method is then validated using a test structure fabricated in a 65 nm SOI process.
Keywords
Delay faults (Semiconductors), Silicon-on-insulator technology.
Sponsors
National Science Foundation
Document Type
Thesis
Language
English
Degree Name
Computer Engineering
Level of Degree
Masters
Department Name
Electrical and Computer Engineering
First Committee Member (Chair)
Plusquellic, Jim
Second Committee Member
Zarkesh-Ha, Payman
Third Committee Member
Pattichis, Marios
Recommended Citation
Aarestad, James. "Characterizing within-die and die-to-die delay variations introduced By process variations and SOI history effect." (2011). https://digitalrepository.unm.edu/ece_etds/1