Electrical and Computer Engineering ETDs

Publication Date

Fall 12-20-2024

Abstract

Field Programmable Gate Arrays (FPGAs) are vulnerable to radiation-induced single event upsets (SEUs) and fault injection attacks, requiring the use of redundancy techniques such as fail-safe computing. Fail-safe computing refers to computing systems that revert to a non-operational safe state when a fault occurs. This work investigates circuit-level techniques and implements fail-safe computing processes as mitigation for SEUs and fault injection attacks on FPGAs. The analysis reveals vulnerabilities that exist in FPGAs over those in application-specific integrated circuits (ASIC); thus, requiring a more elaborate network of redundant circuits and checking logic. The reconfiguration capability of FPGAs adds complexity to fail-safe design strategies by introducing additional fault conditions and propagation paths, via configurable logic blocks (CLBs), PIPs, and other connections and switches. This work addresses the challenges of designing and implementing fail-safe circuits within the fabric of FPGAs. A compact fail-safe circuit design technique called DEsign for Fail-safe in reCONfigurable systems (DEFCON) is proposed. The benefits and limitations of DEFCON, as well as the simulation and hardware results of the fault injection experiments, are presented and discussed.

Keywords

Fail-safe, Field Programmable Gate Arrays (FPGAs), fault detection, redundancy, single-event-upsets, dynamic partial reconfiguration, hardware circuit design, fault tolerance

Sponsors

Sandia National Labs (SNL)

Document Type

Dissertation

Language

English

Degree Name

Computer Engineering

Level of Degree

Doctoral

Department Name

Electrical and Computer Engineering

First Committee Member (Chair)

Dr. Jim Plusquellic

Second Committee Member

Dr. Andrew Suchanek

Third Committee Member

Dr. Payman Zarkesh-Ha

Fourth Committee Member

Dr. Patrick Bridges

Download

Share

COinS