Electrical and Computer Engineering ETDs

Publication Date

12-1993

Abstract

Advances in memory IC technology for dynamic random access memory (DRAM) devices, have been achieved by increasing the number of memory cells occupying a certain chip area, consequently increasing memory size. Current methods of implementation include vertical topography which relies on reducing cell's thickness, while increasing its depth in order to maintain the same capacitance of stored electrical charges. As the memory size on DRAM devices continuously rises, memory cells have to reach deeper levels, thus making the process of measuring depth even harder. This creates a particularly heavy burden on microelectronics manufacturing to research new techniques capable of accurately measuring deep trench depth. A novel metrology technique, which utilizes both two dimensional diffraction analysis and multivariate statistical methods to measure deep trench depth, is discussed in this work. Diffraction analysis involves illuminating DRAM structures with a laser beam and monitoring variations in diffraction order intensity due to variations in trench depth. Multivariate statistical methods establish a relationship between order intensity and trench depth, thus allowing accurate depth prediction. This technique was applied to two DRAM product wafers, and successful prediction of trench depth was obtained for both wafers. Ultimately, the accuracy of this technique was established by comparing our predicted depths to their respective scanning electron microscope (SEM) estimated depths, which gave satisfactory results with an accuracy of ±0.04 µm, or ± 0.56% variation.

Document Type

Thesis

Language

English

Degree Name

Electrical Engineering

Level of Degree

Masters

Department Name

Electrical and Computer Engineering

First Committee Member (Chair)

S. Sohail H. Naqvi

Second Committee Member

John Rasure

Third Committee Member

John R. McNeil

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