Electrical and Computer Engineering ETDs

Publication Date

Fall 11-6-2024

Abstract

Process variations within Field Programmable Gate Arrays (FPGAs) provide a rich source of entropy, making them well-suited for the implementation of Physical Unclonable Functions (PUFs). This dissertation presents three studies on FPGA-based PUFs. First, we explore a ring-oscillator (RO) PUF that leverages localized entropy from individual look-up table (LUT) primitives, analyzing design bias. Next, we investigate delay variations that occur through the routing network and switch matrices of FPGAs using a feature of Xilinx called dynamic partial reconfiguration (DPR). Finally, we evaluate entropy across FPGAs from Xilinx, Altera, and Microsemi using the Shift-Register Reconvergent-Fanout (SiRF) PUF architecture to compare path delay variations and PUF-generated bitstrings. Collectively, these studies provide insights into designing PUF architectures that maximizes entropy levels suitable for cryptographic applications.

Document Type

Dissertation

Language

English

Degree Name

Computer Engineering

Level of Degree

Doctoral

Department Name

Electrical and Computer Engineering

First Committee Member (Chair)

Jim Plusquellic

Second Committee Member

Eirini Eleni Tsiropoulou

Third Committee Member

Patrick Bridges

Fourth Committee Member

William Zortman

Download

Share

COinS