Electrical and Computer Engineering ETDs

Publication Date

5-19-1971

Abstract

1.1 General Aspects of Shift-Register Generated Sequences

An n-stage register is a device consisting of n consecutive two-state memory units controlled by a clock. At each clock pulse, the state ak (logical 1 or 0) of each memory stage, ak, is shifted to the adjacent stage of higher degree. A shift register may be converted into a code generator through introduction of feedback loops that compute a new shift register state based on the previous state of the register. This feedback shift register principle is illustrated in Figure 1-1.

Document Type

Dissertation

Language

English

Degree Name

Electrical Engineering

Level of Degree

Doctoral

Department Name

Electrical and Computer Engineering

First Committee Member (Chair)

Ahmed Erteza

Second Committee Member

Donald Childress Thorn

Third Committee Member

Shlomo Karni

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