Electrical and Computer Engineering ETDs

Publication Date



The maximum dielectric strength distribution of SiO2 in a CMOS structure is shown to be composed of a primary, normal distribution of high dielectric strength and a low dielectric strength group spread through the lower electric field region. The maximum dielectric strength in the primary distribution is within about 0.5 MV/cm of the dielectric strength reported for uniform thickness SiO2 in capacitor studies. This indicates the maximum dielectric strength of SiO2 in a properly fabricated CMOS structure can be nearly as high as the maximum obtainable dielectric strength of uniform SiO2. The primary dielectric strength was not significantly affected by gamma radiation or high temperature stressing with or without electrical bias applied during stress. Processing defects appear more likely to cause significant lowering of the maximum dielectric strength than radiation or high temperature stress. Nearly all of the breakdowns occurred at the gate/field oxide step over p+ regions, most of these over p+ guardbands at the gate metal edge. Breakdowns in these regions are nearly all in the high field strength, primary distributions. Most of the low field breakdowns occurred at random sites in the middle of the gate area, indicating the low field breakdowns are due to a mechanism distinctly different from the primary breakdowns. The current through the SiO2 in the CMOS structure is shown to reasonably fit the Folwer-Nordheim tunneling theory. The current deviates from the tunneling theory near destructive breakdown of the oxide. The data exhibits agreement with the theories that consider Fowler-­Nordheim tunneling current to be the initiating mechanism leading to destructive breakdown of SiO2. Since the current through the gate structure of the CMOS device is close to the theoretical tunneling current of an equivalent area capacitor over uniform oxide, it is concluded that features in the CMOS structure such as gate oxide steps and interfaces with the field oxide do not significantly affect the tunneling current-voltage characteristics of the gate in the field intensity region below dielectric breakdown.

Document Type




Degree Name

Electrical Engineering

Level of Degree


Department Name

Electrical and Computer Engineering

First Committee Member (Chair)

Donald Arthur Neamen

Second Committee Member

Victor Wayne Bolie

Third Committee Member

Roy Arthur Colclaser