Electrical and Computer Engineering ETDs

Publication Date



The first and second generations of infrared detectors—developed from the 1950s to the 1990s—were dominated by single pixel, linear, and staring small format, containing from 1 Kpixels to 100 Kpixels. In the past decade, the third-generation systems presented (a) large format (1 Mpixels to 16 Mpixels), (b) higher operating temperature (200 K to 250 K for MWIR, and 120 K to 150 K for LWIR), and (c) multicolor operation. The emphasis demanded for the next generation of devices is the incorporation of an enhanced functionality in the imagers—preferably at the pixel level—such as color, polarization, and dynamic range control, leading to a dramatic reduction in the size, complexity, and cost of infrared imaging systems. In this work, a new 96 x 96 pixel, 30 um pitch mixed-signal readout-integrated circuit (ROIC) with a pixel-level tunable bias control is demonstrated. The new ROIC is capable of providing a large-bias voltage in both polarities on each individual pixel, independently. These enhanced functionalities are achieved by modifying a capacitive transimpedance amplifier (CTIA) CMOS ROIC architecture. The unit cell electronic circuit was designed using 15 transistors and four capacitors and consists of the CTIA integrator—a two-stage, seven-transistor operational amplifier—one analog memory, one address selector, one reference recover switch, a sample-and-hold stage, an output buffer, and an output multiplex switch. Several test structures of individual devices and complete circuits were implemented on the test chip to characterize each one and to reconstruct the unit cell with discrete components, if necessary. Intending to test, characterize, and control the ITP-ROIC, an FPGA-based hardware and GUI software were developed to generate four analog and 26 digital output signals, with 87 adjustable parameters. In addition to the hardware, chip interconnection techniques were developed to grant nondestructive, flexible, quick interconnections for definition of new test setups. The test chip has been fabricated in TMSC 2P4M 0.35 um high-voltage CMOS technology by MOSIS. With 250 kHz of pixel clock and 57 ms of integration time, the acquired image presents 10 FPS. The ITP-ROIC has a bias voltage range of +/-5 V and an output voltage swing of +/-3.9 V.


Readout Integrated Circuit, ROIC, FPGA-based testing system, Spatio-temporal tunable pixel, VLSI design, Mixed-signal design, Individual pixel voltage biasing, Infrared imaging ROIC, DWELL ROIC, p-i-n-i-p ROIC, IRFPA ROIC


G.R.C.F acknowledges UNM-CHTM, Fulbright and the CAPES Foundation, Ministry of Education of Brazil, Cx. Postal 365, Brasilia, DF, 70359-970, Brazil, for scholarship. The authors also acknowledge the support of the National Science Foundation under grant ECCS-0925757

Document Type




Degree Name

Electrical Engineering

Level of Degree


Department Name

Electrical and Computer Engineering

First Advisor

Krishna, Sanjay

First Committee Member (Chair)

Zarkesh-Ha, Payman

Second Committee Member

Ramirez Fernandez, Francisco Javier

Third Committee Member

Lidke, Keith A.

Fourth Committee Member

Han, Sang