Electrical and Computer Engineering ETDs

Publication Date

2-1-2012

Abstract

The high bandwidth and power needed to process the data coming from modern high resolution focal plane arrays leads to the necessity for fast and efficient read out and data processing. A system that performs block recognition and image classification with efficiency and low latency is presented. The system is comprised of an analog signal processor that will be integrated into the read out integrated circuit. This enables the capability to read out the focal plane array information and process it completely in the analog domain in a comparably very small amount of operational steps. The steps and techniques of the design flow, including definition of problem, concepts and design of system architecture, simulation of system, and analog lay out practices are covered.

Keywords

Signal processing -- Equipment and supplies., Image processing -- Equipment and supplies., Linear integrated circuits.

Document Type

Thesis

Language

English

Degree Name

Electrical Engineering

Level of Degree

Masters

Department Name

Electrical and Computer Engineering

First Advisor

Zarkesh-Ha, Payman

First Committee Member (Chair)

Plusquellic, James

Second Committee Member

Graham, Edward

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